Abstract
Threshold voltage Vt extracted by gm-maximum extrapolation method under early stage hot carrier stress is proven to be an inappropriate method once electrons are trapped in nitride spacer. The trapping of electrons in nitride spacer increases the series drain resistance, reducing the transconductance gm and the corresponding gate-to-source voltage Vgs at which peak gm occurs. It ultimately decreases the threshold voltage Vt extracted by the gm-maximum extrapolation method. A novel algorithm is derived to determine the relationship between the measured data and the true threshold voltage of such a device under hot carrier stress, by considering the effect of series resistance on gm-maximum extrapolation method.Spacer bottom oxide in the nitride spacer LDD device, which is used to prevent huge interfacial states between nitride and silicon interface, plays an important role in the hot carrier test. Because of the stress due to atomic size mismatch between nitride spacer and silicon, trap-assisted hot electron tunneling is more serious in nitride spacer LDD device than oxide spacer counterpart. Thicker bottom oxide can eliminate this effect. However, the optimized thickness of nitride spacer bottom oxide should be varied for different poly-silicon gate structure. The hot carrier stress in nitride spacer LDD device perform multi-stage degradation under Isub,max stress. It is dominated by electron trapping at the early stage, interfacial states (Nit) creation for the second stage, and self-limit hot carrier degradation at the last stage. The degradation for Ig,max stress in nitride spacer LDD devices is mostly contributed by electrons trapped in nitride/oxide interface.The traditional hole traps and neutral electron traps caused by hot hole injection in low gate voltage stressing (Vgs = 1/5 Vds) no longer exist in ultra thin oxide (~ 2.0 nm) NMOS transistors. An electron injection is applied right after low gate voltage stress, however, there is neither enhanced hot carrier degradation nor “kink” existing in time-dependent increasing interfacial state ΔNit curve. Without hole traps, the damage of low-gate voltage stressed ultra thin oxide NMOS transistor is contributed by interfacial states Nit only. The bias range of interfacial states dominated only in hot carrier stressing is expanded from Vgs = 1/2 Vds to Vgs = 1/5 Vds, instead of the range which is around Vgs = 1/2 Vds for thicker oxide devices.The simple guideline that use Isub change to determine the hot carrier damage type is no longer suitable in ultra-thin oxide device. Because only small portion of hot carrier damages located within pinch off region, in which the damage is not impacted device operation, the drain current degradation in saturation region is approaching to current degradation in linear region. It consequently increases substrate current degradation in low gate voltage. The smaller pinch off length is produced in ultra-thin oxide device because of scaling of drain operation voltage (1.2 V).Hot carrier degradation in ultra-thin oxide device under medium gate voltage stress are contributed by both hot carrier impacted ionization and electron-electron scattering (EES). In medium gate voltage range, device degradation rate increases as gate voltage increase. It is contributed by the change of damage position toward LDD edge when gate voltage increases.As ultra-thin oxide device under high gate voltage stress, surface EES dominates the hot carrier behavior and results in the worst device degradation. The change of bulk EES to surface EES is the results of potential difference between gate and drain, the squeeze potential of contour near drain edge is reduced as gate voltage increase. In high gate voltage stress, the self-limited hot carrier degradation occurred at the beginning of hot carrier stress. The defect location moves away from LDD edge as stress time increasing.