Abstract
自1961年，金氧半電晶體發明以來，其製程技術漸受肯定，與雙載子電晶 體件相較，金氧半電晶體元件具有低成本、高生產密度等優點，另外在操 作速度及功率消耗等方面亦有其可取之處。近年來積體電路已進入超大型 積體電路的階段，而金氧半電晶體製程技術也已進入次微米，甚至毫微米 的製造技術，其中元件縮小化技術扮演相當重要的角色。元件的縮小化主 要是受限現有的製程技術及元件縮小後特性的可操作性及可靠度。為解決 此元件可靠度的問題，一般工業上的做法是在汲極端加上大角度離子佈植 淡摻雜結構，降低汲極端的高通道電場。但是汲極大角度離子佈植淡摻雜 結構雖可有效解決可靠度問題，卻因元件為對稱型架構，所以同時引發出 輸出電流降低及更嚴重的短通道效應。如何最佳化設計源/汲極端大角度 離子佈植淡摻雜結構，則為本篇論文所探討的重點。 最後，為解決在設 計深次微米源/汲極端大角度離子佈植淡摻雜結構中所遭遇到的瓶頸，提 出一淺源極淡摻雜汲極(Shallow Source Lightly Doped Drain - SSLDD) 之新元件結構，並比較淺源極淡摻雜汲極元件相對於源/汲極端大角度離 子佈植淡摻雜元件、傳統式陡接面元件的相異處及改進的地方。 Owing to the device structure and quite stable process technology, MOSFET features higher dense capacity and lower cost in manufacturing, lower power consumption and higher speed in operation than bipolar device. Recently, the development of deep submicron device plays an important role in ULSI era. The device scaling methodology with the compromise of device performance and device reliability becomes indispensable in ULSI improvement. There exists several methods in improving the device reliability. The employment of Large Angle-Tilted Ion- implanted Drain (LATID) reduces channel electrical field at the drain side and thus relieves the reliability issues. However, symmetrical LATID structure encounters lower output current and more serious short channel effects. In this thesis, the LATID optimization based on the trade-off between device performance and reliability is studied in detail. Besides, we also propose Shallow Source Lightly Doped Drain (SSLDD) structure to solve the bottleneck in optimization of deep submicron LATID structure. Finally, we would demonstrate the improvements in SSLDD and the comparisons between SSLDD, LATID and conventional abrupt junction devices.