Abstract
Owing to the device structure and quite stable processtechnology, MOSFET features higher dense capacity and lower costin manufacturing, lower power consumption and higher speed inoperation than bipolar device. Recently, the development ofdeep submicron device plays an important role in ULSI era. Thedevice scaling methodology with the compromise of deviceperformance and device reliability becomes indispensable in ULSIimprovement. There exists several methods in improving thedevice reliability. The employment of Large Angle-Tilted Ion-implanted Drain (LATID) reduces channel electrical field at thedrain side and thus relieves the reliability issues. However,symmetrical LATID structure encounters lower output current andmore serious short channel effects. In this thesis, the LATIDoptimization based on the trade-off between device performanceand reliability is studied in detail. Besides, we also proposeShallow Source Lightly Doped Drain (SSLDD) structure to solvethe bottleneck in optimization of deep submicron LATIDstructure. Finally, we would demonstrate the improvements inSSLDD and the comparisons between SSLDD, LATID and conventionalabrupt junction devices.