Abstract
In this thesis, we present a mixed-level methodology for estimating the peak power dissipation of a logic IC. The ultimate goal is to mix the speed of a logic simulator with the accuracy of a transistor-level simulator. There are two major techniques in this methodology. Firstly, we attempt to establish the delay correlations of two simulators at different level of abstractions through a technique called delay calibration. Secondly, we use simple waveform shaping to re-generate the accurate waveforms of signals based on the calibrated delay information. By doing so, the time-consuming simulation at the transistor level can be skipped without losing much accuracy. Experimental results on a number practical design block shows that it is 30% more accurate than a pure gate-level simulator on the average.