Abstract
In recent years, SoC design improves quickly and becomes more and more complex. Since manufacturing technique of fabrication must follow the improvement of circuit design, many problems are generated during this improving progress. One of them is on-chip interconnect induced issue, which is related to parasitic resistance, parasitic capacitance, and parasitic inductance. And it is regarded as future main bottleneck of circuit design due to its bad influence on the performance of global circuit. In the past, circuit designers just considered the effects of parasitic resistance and parasitic capacitance. But the speed of chip will achieve several GHz, parasitic inductance will become very important. If we don’t consider the parasitic inductance, we will loose the accuracy while doing simulation and the chip will fail. In this thesis, we will use FastHenry as our standard of inductance simulation, use different structures of transmission line, and propose our method to build inductance table then. We discovered the inductance is monotonic in experiment results. So, we conclude that applying interpolation to calculate the inductance which is not in this inductance table will work in the case. Though there are more complex transmission lines in real circuit, one can use simple algorithm to get simulated inductance with negative errors based on the inductance table here which covers many kinds of transmission line structure. In addition, we also proposed a method on this application and explain why the errors are negative. In conclusion, on-chip inductance table will be useful for circuit designer to design critical transmission line. In the future, we can propose more transmission line structures with self and mutual inductances for circuit designer and use 90nm silicon wafer measurement such as S-parameter to prove FastHenry is accurate in nanometer inductance extraction.