Abstract
Reference circuits have been studying for many years. Following the vigorous development of portable electronic products, integrated circuits with low voltage and small area have become the core part of the recent research. Parasitic vertical bipolar junction transistors are commonly used in CMOS voltage reference circuits for a better stability. Recently, MOS reference circuits have been used to replace BJT ones in order to reduce the chip area and supply voltage. Whether BJT or MOS is utilized, the problem that resistances parallelizing on either side of BJT or MOS generally occupy quite large ratio of chip area under the consideration of power consumption and loading parasitic capacitances of op-amp still exists. Another problem worthy of our concern is that spurious signals coming from the supply voltage cannot be adequately rejected and may couple into the circuit to degrade output signal in high frequency applications. This thesis aims to improve the above problems and proposes a novel voltage reference circuit. A current mirror is designed for temperature compensation and large resistors are defeasible for reduction chip area. Besides, it has been implemented by a 0.18 μm CMOS process with a chip area of 0.023 mm2. Simulation shows that the variation of temperature coefficient is from 59.5 to 63.8 ppm/℃ under the temperature range from -40 to 100 ℃ and a supply voltage variation from 1.2 to 1.98 V. The power noise rejection ratio is -70 dB at 10 kHz with 1.2V supply voltage. In summary, the thesis adopts a current mirror to achieve low-temperature-drift reference voltage and abandons large resistances on design consideration. With this approach, power noise rejection ration is reduced.