Abstract
The HOY project proposed a new methodology of IC test to use RF wireless channels to transfer data instead of probe cards in traditional ATE. Even though the goal of a HOY system is to reduce the test cost, it also introduces the unreliability factors of RF communication into the tests. In order to characterize effects by HOY modules before production, we propose to add an additional wired interface to DUTs. The new interface is compatible to IEEE 1149.1 JTAG, which reduces the effort to integrate with package tests. Because of the relatively simple architecture of a HOY system and JTAG, the added interface consume only 5.8K gates (in addition to HOY modules). Both RTL simulation and FPGA prototype are used to verify the new interface. Besides the role of characterizing tests for HOY, we can also use the interface to complement the usage of HOY modules. For example, HOY wireless tests can be used in wafer sorts, while the wired interface can then be utilized in packaged tests, and finally wireless channel can be used again in field test/diagnosis. 1