Abstract
With the rise of consumer electronics and handheld devices, electronic packaging becomes lightweight, smaller, high I/O and high-power. For example, the use of solder balls of ball grid array (BGA) package gradually replaces Quad Flat Package (QFP) in order to increase the I/O counts. In recent years, Wafer Level Chip Size Packaging (WLCSP) catches everyone's attention due to its small size. Both WLCSP and BGA use solder balls to connect die and the substrate, but the difference is that WLCSP is packaged directly on a wafer and it doesn’t need the wire bonding and underfill but buffer layer. The purpose of buffer layer is to increase the mean time to failure of the solder ball which is due to the CTE mismatch between the chip and the substrate. The thermal cycling test is a standard method which is currently used to characterize the reliability performance of electronic packaging. The test vehicles are placed in a condition which is harsher than the actual usage condition in order to reduce the testing and development time. Then use the acceleration factor to predict the fatigue life which is under original test condition, so acceleration factor must be accurate. Using the finite element simulation with a few experiments can reduce the testing time again. The original acceleration factor model was proposed by Norris and Landzberg which includes temperature range, temperature-cycling frequency and the maximum temperature. In this research, the three terms maximum temperature, temperature range and frequency will be modified, and compared with experimental results. To investigate the maximum temperature term, thermal cycling test condition refers to JEDEC standard in which the temperature range is between 0°C to 125°C while the others are -10°C to 115°C and -20°C to 105°C. To investigate temperature range term, thermal cycling test condition refers to JEDEC standard which the temperature range is between -40°C to 125°C and others are -20°C to 105°C and 0°C to 85°C. The frequency term will be discussed by dividing into ramp rate and dwell time. Because Norris-Landzberg acceleration factor is only feasible for BGA type package, a simulation model of wafer level chip scaling package is constructed in this research. Because the temperature under accelerated thermal cycling test always exceeds one third of the melting point (in Kelvin) of the solders, the creep effect becomes ineligible and needs to be considered. In this study, Garofalo Hyperbolic Sine Model is used to simulate the creep behavior of the lead-free SnAg solder alloy and kinematic hardening model is used to simulate the plasticity behavior. In this study, two life prediction models are selected to investigate the reliability of WLCSP. One is Coffin-Manson strain based model and another one is Darveaux energy based model. The simulation results show that the increment of creep strain energy density has changed insignificantly, so the fatigue life does not coincide with the experimental results when Darveaux model is applied. However, the increment of creep strain increases with the increase of maximum temperature which is same as the experimental result. Therefore, Coffin-Manson strain based model is applied to modify the maximum temperature term in the original acceleration factor model. Finally, compare our complete modified acceleration factor model with the experimental results under arbitrary temperature, and it shows that our acceleration factor model is more accurate than the original N-L acceleration factor model.