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用於WLAN 802.11a 射頻接發機之CMOS頻率合成器
Thesis

用於WLAN 802.11a 射頻接發機之CMOS頻率合成器

姚澤華
Masters, 國立清華大學, 電子工程研究所
2002

Abstract

頻率合成器 壓控振盪器 synthesizer vco
The goal of this work is to use TSMC 0.18μm CMOS process to implement a PLL-based frequency synthesizer with a monolithic LC-tank voltage-controlled oscillator. The building blocks include phase frequency detector, charge pump, loop filter, voltage-controlled oscillator and programmable divider. A new structure that can generate higher negative resistance is proposed. We use this new negative resistance circuit to implement LC-tank voltage-controlled oscillator. The simulated negative resistance of this new structure is -259.8 Ω. The simulated negative resistance of conventional structure is -152.7Ω. . It allows the circuit to take less time to become oscillation. A quadrature oscillator is also implemented by this new negative resistance circuit. It can support quadrature outputs without any digital circuit. The simulated negative resistance of the new structure is -272.1 Ω. The simulated negative resistance of conventional structure is -141.5Ω. In addition, a new low flicker noise transistor layout is proposed. It can reduce the effect of flicker noise for phase noise. Better phase noise of a monolithic LC-tank voltage-controlled oscillator is obtained.

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