Abstract
Department: Electrical Engineering Title: A SAR ADC Design for Monolithic CMOS Radar System Advisor: Prof. Ta-Shun Chu Graduate student: 9861627, Liu-Yuan Yu With the progress of the silicon process and yield enhancement, system on chips are increasingly easy to implement compared to the original design of the past use of discrete systems. It is increasingly popular in the system on chip. The circuit is composed of analog and digital parts. In order to connect analog and digital, you need an analog to digital converter. The successive approximation analog-converter with low voltage consumption is a good choice for a system. This thesis presemts three different successive approximation analog-converter, to explore the differences and advantages and disadvantages.Which, respectively, for synchronous and asynchronous timing, monotonic and conventional successive approximation type algorithms in different architectures of successive approximation analog converter design and discussion. We will implement it by TSMC 180-nanometer, TSMC 90-nanometer and UMC 180-nanometer process to achieve all the design blocks. And then according to performance characteristics make a simple conclusion. Different architectures of SAR ADCs are proposed and implemented in silicon technologies. These ADCs are designed with different sampling speed and resolution in order to be integrated in Radar systems. Two radars systems adopt the implemented ADCs. One is a 3-5GHz UWB impulse radio radcar system for human feature detection and the other is a W-band mm-wave vehicle radar system. The input signals are in radio frequency and the output signals are in digital domain in the receivers of the radar systems. These reduce the complexity of the package and intrerface. The simulated performances of these ADCs are following. The TSMC 90nm 8-bit SAR ADC achieves 5MHz sampling rate and 46dB SNDR. The TSMC 180nm 8-bit SAR ADC achieves 1MHz sampling rate and 52dB SNDR. The UMC 180nm 7-bit SAR ADC achieves 50MHz sampling rate and 36dB SNDR.