Abstract
AbstractFor many high-performance IC designs, the verification of timing is essential yet challenging. After manufacturing, certain defects may cause some chips to fail in timing. In order to improve the manufacturing yield and shorten the time-to-production, delay fault testing and diagnosis is often necessary. Delay diagnosis has been a topic of extensive research both in industry and in academia. Several delay fault models and testing methodologies have been proposed. However, these methods are not adequate in terms of the accuracy.This thesis introduces a new algorithm for gate-delay fault diagnosis. It is based on the inject-and-evaluate paradigm [1], in which the fault site(s) are predicted through a series of injections and evaluations. Unlike the backtrace algorithm that predicts the fault site by tracing the syndromes at a faulty output back into the circuit, this approach mainly relies on the six-valued simulation. In such a forward approach, the accuracy is much higher because all the composite syndromes at all faulty outputs are considered simultaneously. We also analyze the effects of glitches and take them into account in our algorithm. As a result, the proposed approach is still applicable even when there are glitching outputs or when the delay size is relatively small. Experimental results show that the number of fault candidates produced by this approach is only 4.8 within 10 seconds of CPU time.