Abstract
Flash memory, as its rapidly increasing demand recently, suffers from the reliability issue. However, due to its non-volatile nature, error correcting codec (ECC) are widely adopted for flash memory. In this thesis, we design the error correcting codes, including low-density parity-check (LDPC) and Bose-Chaudhuri-Hocquenghem (BCH) codes for flash memories. We also establish an evaluation framework for the performance analysis among different ECCs. To optimize the design parameters of the hybrid codes that integrate LDPC and BCH codes, we evaluate the existing hybrid technologies for error correcting scheme of the non-volatile memory. We target at the specification of a flash memory with realistic spare capacity and timing requirement. Considering the practical hardware implementation, we design and evaluate quasi-cyclic (QC) LDPC codes. The cyclic encoding and turbo-decoding messagepassing (TDMP) algorithm are analyzed as the encoding and decoding algorithm. With the evaluation result for the proposed flash memory system, the hardware architecture of the encoder and decoder are also presented. Finally, the comparison of the proposed architecture with other works is made. The memory usage of our decoder can be as low as 10% of previous work, while the decoding cycle is within the specification of the flash memory system. The result shows that our hybrid LDPC and ECC scheme is efficient for non-volatile memory. Our future work include the study of Euclidean geometric (EG) LDPC codes, the improvement of the encoder and decoder architecture and the construction of specific error model of dedicate the non-volatile memory.