Abstract
AbstractThe wireless communication integrated circuits design prevail in the last decade due to the advances of semiconductor process and DSP. Image-reject architectures are frequently applied to alleviate the image interference induced in dual frequency down conversion receivers. Ideally, image-reject receivers can achieve infinite image rejection ratio (IRR). Process variation, however, causes unpredictable phase and gain mismatches in signal path and degrades the corresponding IRR. Good layout planning, in general, can attain around 40 dB IRR, this is not sufficient to fulfill stringent system requirement without other filter used.In this thesis, a novel calibration technique named DC Detection is proposed to improve IRR performance. The calibrated technique is used in analog domain avoiding power consumption of ADC. At start of calibration, an image signal is fed into the receiver, after dual frequency down conversion, lead out an output DC voltage to represent the degree of gain and phase mismatch of the receiver. Extensive simulation results indicate that the IRR performance can be improved from 25dB to 70 dB with small circuit overhead. The additional power and time consumed by calibration are less than 1mW and 100us, respectively.