Abstract
By modeling the charge injection and emission mechanisms in a SONOS device, the change of trapped charges in the silicon nitride layer as a result of gate bias voltage can be predicted. A simulation program based on these models is built, which allows us to simulate programming and erasing characteristics of a SONOS device. With this simulation program, we could investigate the programming and erasing characteristics of a SONOS device as the device parameters, such as top-oxide thickness (XOT), nitride thickness (XN), bottom-oxide thickness (XOB), trap density (Nt), centroid position of charges and operation voltage, changes. Thereafter, better SONOS structure and operation conditions can be designed to meet the need of a specific application in operation speed, lower power consumption or better retention of an memory product. In this thesis, the phenomenon of gate-voltage-dependent threshold voltage saturation when erasing, which has not been well explained by any theoretical model is also addressed. By introducing the image force barrier lowering effect in this simulation program, this phenomenon can be well explained.