Abstract
A hybrid architecture is described as an alternative solution to sigma-delta fractional-N frequency synthesizer for wireless communication. A direct digital frequency synthesizer (DDFS) is wellknown as its high frequency resolution and fast settling, while a phase lock loop is more likely to be used at high frequency. This architecture takes the advantages of both synthesis method and is designed for a DCS-1800 communication system. The synthesizer is implemented primarily as a PLL. For small channel spacing and short settling time specifications, the reference frequency must be set high to acquire larger loop filter bandwidth. The fractional division is then necessary to decouple the frequency resolution and the bandwidthsettling requirements. Instead of a sigma-delta modulated multi-division divider [1] [2], DDFS serves as an direct digital fractional divider. The DDFS core is further modified by a sigma-delta modulated accumulator (SDMA) to save more power and area. Measured results from a prototype shows good match to the simulation. The key circuits were implemented on a 0.18um CMOS techonology. Hspice simulation indicates only moderate power and area are required.