Abstract
In this thesis, a high density 3D-stacked Via RRAM compatible with CMOS logic process without any extra mask has been proposed. This novel resistive-memory device has been demonstrated successfully both in the Al-based backend process and the Cu-based backend process. Under the Al-based backend process, RRAM consists of TiON is fabricated between W top electrode and AlCu bottom electrode. Ti and TiN are commonly adopted as the barrier layer to prevent the diffusion of AlCu alloy. TMO layer is automatically formed during BEOL manufacturing steps. In the Cu dual damascene backend process, RRAM consists of TaON is stacked between two Cu electrodes. Similarly, Ta and TaN are usually adopted as the barrier layer to prevent Cu diffusion. By arranging WLs and BLs in the orthogonal direction, a high-density and cross-point RRAM array was successfully demonstrated. A vertical 1D1R bit cell driven by a TaO-based oxide diode is fabricated by layout adjustments. The influence of sneak current path in the cross-point array can be severely suppressed by adopting 1D1R cell structure. Comparing 1T1R and 1BJT+1R cells, the Via RRAM 1D1R cell is multi-layer stackable, and lower cost. We believe that the novel 3D-stacked Via RRAM has high potential in the applications of storage-class embedded NVM.