Abstract
The purpose of this research is to integrate a high-performance pixel architecture which designed by our laboratory, an analog to digital converter (ADC) and peripheral circuits in chip. It can reduce noise, save chip area, and easily be applied to the multi-function consumer electronics. Therefore, this study will design a front-end circuit for a Full HD camera-on-chip system with 30 frames per second, wide sensing dynamic range in standard TSMC 0.18μm SiGe BiCMOS technology. Considering the demand of higher pixel resolution in the future, this paper presents a CMOS imager with column-level ADC. The implemented ADC uses a single-slope architecture which features high linearity, simple structure and low power consumption. Design of resolution is 10bit, sampling rate is 50kHz, and power consumption is less than 150uW for each column.