Abstract
With the scale down of flash memory devices in recent years, several approaches such as poly-Si channel, SiGe channel, junctionless architecture, stacked gate dielectric and nanowire structure have been proposed to improve the device operation characteristics. In this thesis, Sentaurus TCAD (Technology Computer Aided Design) simulation tool is used to study planer (2D) and tri-gate (3D) flash memory devices. Effects of Si/Ge channels and stacked tunneling layers with GeO2/Al2O3, SiO2/Al2O3, GeO2/SiO2 and GeO2/Al2O3/SiO2 on 2D and 3D charge trapping flash memory devices are investigated and compared. In the first part, simualted operation characteristics of planer poly-Si and SiGe channel charge-trapping flash memorys are compared to experimental ones. Results show that the trend of the simulation and experiment results are not consistent. Therefore, the physical parameters of tunneling layer of SiGe channel device are modified, and then the simulated results are compared with those of poly-Si channel device. Faster program/erase speeds are achieved by the modified parameters of tunneling layer of SiGe channel device, which shows the same trend as experiment results. The retention characteristics of poly-Si and SiGe devices are similar due to deeper energy level of traps in the trapping layer. In the second part, tri-gate structures are employed in flash memory devices to simulate operation characteristics because they are exactly used in the experimental devices. Operation characteristics of devices with poly-Si channel and those with SiGe one and modified tunneling layer parameter (MPSiGe) are compared. MPSiGe devices show faster program and erase speeds but worse retention characteristics than poly-Si channel ones. Furthermore, it is found that program/erase speeds of devices with tri-gate structure are faster as compared to those with planer ones because of higher injection efficiency. The influence of tunneling barrier is larger than that of tri-gate structure. Therefore, operation performance of flash memory devices can be enhanced by appropriate tunneling barrier and tri-gate structure. In the third part, stacked tunneling layer on operation characteristics of junctionless flash memory devices with Si/Ge channel are studied. The program/erase speeds of devices are faster because of lower channel barrier, thinner physical thickness of tunneling layer, and stacked tunneling layer with lower dielectric constant materials. Slow erase speed and poor retention characteristic of devices are due to thinner physical thickness. In order to obtain acceptable performance for all operation characteristics, device with three-layer stacked tunneling oxide is studied, and its results are compared with those of device with two-layer one. Device with three-layer stacked tunneling oxide shows better operation characteristics due to its appropriate physical thickness and stacked structures.