Abstract
硬體模擬器(Hardware emulator)由多個現場可程式化閘陣列(FieldProgrammable GateArray)所組成，是為了模擬電路的正確性，然而腳位數的限制卻使邏輯使用率偏低． 虛擬線路藉由時間分隔多工(Time-Division-Multiplexing) 增加了 FPGA 和 FPGA 之間信號傳遞的頻寬，使得多條虛擬線路可以共用一條實體線路． 如此一來，硬體模擬器中每個現場可程式化閘陣列所使用的邏輯使用率(Logic Utilization)可因此而提高．而對於信號的傳輸加以適當的時間分配(Phase Assignment) 可以減少線路所需的模擬時間．硬體模擬器連接的架構大致可分為網狀連接(mesh interconnection)及部份交叉連接 (partial crossbarinterconnection)這兩種架構，而我們接下來所有的討論都是針對網狀連接這樣的架構底下來進行我們的討論．在這篇論文中，我們提出一個方法來更加減少模擬線路的時間． 方法包括了繞線(Routing)以及定位(Placement)兩方面， 我們結合這兩方面來減少臨界路徑 (CriticalPath)的長度， 再加上對信號作適當的 Phase Assignment ，使得模擬線路的時間得到相當程度的降低．其中，在繞線部份，我們把所有的等電位(Equal Potential)的網路(Net)用從源頭(Source)到終端(Sink)最短的方式來繞． 其次，在 placement 部份，我們把在 critical path 上的每個 net 的源頭細胞(source cell) 的幾何位置加以改變，使得critical path 越直而長度因此而縮短．A hardware emulator consists of multiple FPGAs interconnectedto emulatethe given design circuit. The biggest problem withhardware emulator is that the logic utilization for each FPGA israther low due to the fact thatpin count provided by currentFPGA packaging technology can not keep the samepace as the logiccapacity, so the logic utilization is limited by the pin count,which leads to the so-called Pin-Limitation problem. Virtual-Wire technology overcomes Pin-Limitation by multiplexingmultiplelogical wires over a physical wire in a Time-Division-Multiplexing fashion.The architecture is to parallelly outputsignals from certain FPGA toa group of shift registers and drivethese signals one at a time serially to a physical wireconnecting neighboring FPGAs, then neighboring FPGAs convertthose serial input signals to parallel input signals byanotherset of shift registers.We propose, in the thesis, a system thatcombine a proper way of scheduling signals, which is termedPhase-Assignment, with routing and placement refinement tominimize the emulation cycle time.