Abstract
The Magnetic Random Access Memory (MRAM) is considered one of the potential candidates that will replace current on-chip and commodity memories (SRAM, DRAM, and flash memory) in the future. MRAM combines advantages of RAM and flash memory, making it a potential choice for system-on-chip (SOC). There are few MRAM products on the market presently, but this does not imply the test issues of MRAM are solved. For assuring the quality and yield of MRAM, we present the Write Disturbance Fault (WDF) model for MRAM, which is justified by chip measurement results. We also present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. To identify WDF, an Adaptive Diagnosis Algorithm (ADA) is developed for fault diagnosis. We also construct the SPICE model of toggle MRAM array from the magnetic tunneling junction (MTJ) device model of ERSO* to obtain circuit simulation results for WDF testing and diagnosis. Finally, we design an MRAM BIST circuit with WDF diagnosis capability, and a particular BIST implementation method which utilizes the Read-before-Write mechanism is proposed to reduce overall test time. The experimental results from circuit simulation and RAMSES-M show that the March C- test algorithm detects WDF, and March-17N diagnosis algorithm distinguishes the WDF from conventional faults. Also, circuit simulation result justifies that the adaptive diagnosis algorithm is useful for diagnosis of a WDF cell. Finally, BIST circuit has only 0:75 % of hardware overhead for a 1-Mbit MRAM, and test time is further shortened for the toggle MRAM. *Electronics Research and Service Organization, Industrial Technology Research Institute, Taiwan