Abstract
As product requirement moves from digital microprocessors and application-specific integrated circuits (ASICs) to system-on-a-chip (SOC), process encounters complex functionality integration, more heterogeneous systems, and the challenges of providing a diverse range of components on a single chip. These trends push the process to provide multiple power supply and scalable hierarchy interconnect scheme, which lead the number of mask set increases from 10s to 40s layers. Being the key role and driver of the process development, test vehicle design will be under the light spot of these challenges. To reduce the complexity and provide a traceable flow for process development, we explore a methodology, which is test vehicle driven process development.Starting with the scaling principle and prediction of design rule, a concise test chip design plan can be hierarchically derived. The scaling principle compromises the existing equipment and the future needs. A Monte Carlo simulation links the in-line data and the process capability to predict the design rule prior to the process development of next generation. The design rule prediction methodology changes the scaling principle from the direct shrinking approach to the adaptive, which enable the design rule much more tolerance to the process variation and fluctuation.To provide an efficient test structure design in the limited test vehicle, the addressable failure site test structure (AFS-TS) is proposed. The graph terminology is used to analyze the spatial correlation between the test structure and the probe pad configuration, thus, an optimal solution for the test structure is derived. To validate the design methodology, four ASF-TS types are designed and implemented for 0.25 μm generic logic process and high performance process with low-K dielectric. In the meantime, the application for defect detection and reduction is discussed and the potential application as the assessment of wafer uniformity profiling is explored. The application for SRAM memory cell optimization is presented to adopt the consideration of defectivity at the beginning of process development. A statistical methodology is presented to simplify the data representation and reduces the complexity of the modeling. With the feature of principal component analysis, the correlated in-line metrology data and electrical test of the test structures can be mapped into a principal component set of which each vector is independent. The raw data can be represented as the limited linear combination of principal component, thus the parameter of device modeling can be dramatically reduced.