Logo image
積體電路設計前期的暫存器傳輸層設計探索
Thesis

積體電路設計前期的暫存器傳輸層設計探索

謝智光
Masters, National Tsing Hua University
1998

Abstract

暫存器傳輸層設計空間探索時序分配面積-時間曲線預估 RTLDesign Space ExplorationTiming-BudgetArea-Time CurveEstimation
In this paper, we present an RTL design space exploration method for early designplanning. We formulate the RTL design space exploration into a performance-diventiming-budget assignment problem. We present a dynamic programming algorithm anda heuristic to solve the problem. We also present an integrated RTL/logic synthesisand physical design flow to perform RTL design space exploration. Experimental resultshave demonstrated that the proposed method can effectively perform design spaceexploration at RTL.

Metrics

1 Record Views

Details

Logo image