Abstract
The proposed instruction set test program aims the at-speed functional testing for pipelined processor core. If the processor design is based on Harvard structure, the proposed method can provide effective method to extract the constraints for functional level testing. Especially for the pipeline structure, the processor can be divided into several blocks, and each block can be individually analyzed. By observing the register bank and pipeline register, the proposed methodology provides an automatic and efficient flow to generate the test for the targeted fault with an instruction-level simulator and a gate-level ATPG. In this thesis, through instruction-level simulator, a flexible mechanism is provided to extract functional constraints of each pipeline stage to minimize unnecessary backtracking on internal signals imposed on gate-level ATPG. Given the generated constraint graph and additional user definitions, the test program can be synthesized by analyzing the correlations among general/pipeline/status registers, control signals, and constraints can be extracted. Applying the technique to the ARM 7 compatible processor core, such extracted constraints are applied to efficiently reduce the length of test patterns for identifying functional faults and to illustrate how to use generated constraint graph for each pipeline stage for integrating tests for the processor core.