Abstract
In recent years, using reusable cores, i.e., pre-design Intellectual Property (IP) blocks, to shorten the time-to-market for new ICs has become the most popular design methodology. In order to prevent test development from becoming the bottleneck in the entire design flow, the use of the pre-computed test patterns for the embedded cores is necessary.In this thesis, we propose a hierarchical test access architecture and an automatic test development flow. The proposed architecture is compliant with P1500, JTAG and hierarchical cores. By using the proposed Test Interface Controller, the cores which are deeply embedded into system orother hierarchical cores can be accessed through the test pins, and the use of the pre-computed test patterns becomes a very easy work. The proposed automatic test development flow cludes the Test Circuit Generation Flow, P1500 Compliant Test Pattern Translation Flow and Test Pattern Integration Flow. For these flows, we also develop some softwares to facilitate the test development procedure to shorten the development time cost.We also utilize some ISCAS benchmark circuits to implement a experimental circuit. Based on experimental results, we can find that both the area overhead of the Test Interface Controller and the effective test time overhead are small.