Abstract
It has been a hard problem to locate the fault sites in an IC that does not pass the manufacturing test. A diagnosis tool will help a lot to narrow down the suspect region and to ease the burden of failure analysis engineers.Several types of diagnosis methodology have been proposed. Cause-effect approach build up a fault dictionary then look up the dictionary for the faulty syndromes to find the fault sites. This type of approaches rely on specific fault models and the size of fault dictionary may be too huge to build. Symbolic approaches are able to address multiple faults ccurately. Unfortunately, they are only suitable for design error and weak on handling large circuits. Simulation-based approaches can be used in large circuits, but their diagnosis resolution are not so good due to fault masking and fault signature aliasing. This thesis introduces an efficient double faultdiagnosis scheme for combinational circuits. It is a fault-simulation based approach which contains a technique to shrink the candidate pair list and an exact diagnosis method based on cure injection to pin-point the real fault pair. The new candidate pair list, which is much smaller than all possiblecandidate pairs, is generated by an effective heuristic. Then, the exact double fault diagnosis method is applied to find the actual fault sites. This heuristic can reduce the time complexity of diagnosis from O(N^2) to O(N). Experiment results show that the diagnosis time can be dramatically reduced, while the rate of successfully identifying the faults remains high.