Abstract
Semiconductor memories play an important role in modern System-on-Chip (SoC) designs, including RAM and Flash memory. Semiconductor memory testing thus has been a key problem in testing integrated circuits for years. With their growing density and capacity, the test time grows rapidly if the test methodologies and equipments remain the same. Test time reduction other than parallel insertion—which is expensive and more and more difficult to keep up with the memory capacity growth—is a long time researched issue, as test cost is directly related to the time each product stays on the tester. Furthermore, we also need more design-for-testability (DFT) circuits to reduce the memory test time in the SoC era. The designers need to pay more attention to designing the DFT circuits. In this thesis, there are two parts devoted solving the memory testing issues discussed above. One is semiconductor memory test time reduction. We propose a systematic pproach to analying and rearranging the test items in the test flow. We propose two test compaction techniques: 1) merging existing test patterns, 2) developing efficient new test patterns. The proposed test time reduction algorithm is shown to effectively reduce the test time of an industrial DRAM test flow. The test time reduction tool also can identify the redundant test items, suggest a proper test list, and provide the correlation between the test items. In the industrial case, an extra 7% of the total test time is further reduced, on top of the original manually compacted test flow. The other is the Flash memory built-in self-test (BIST) circuit generator. This generator can generate synthesizable BIST RTL code in Verilog, and the generated BIST can combine with RAM BIST that is generated by a RAM BIST generator (called BRAINS). Besides, the generated BIST architecture supports paralled testing of multiple Flash memory cores to reduce test time in SoC.