Abstract
Over the past decade, due to the continuously decreasing feature size of processor design, the power density on chip has increased drastically. From one generation of processor to the next one, the price we paid for doubled frequency is the doubled power consumption. Solutions to save power not only lies in hardware, but also lies in software. Power consumed by the same processor varies when different programs are running on it. There are a lot of opportunities for compiler to exploit the low power features and generate power efficient code. More synergy between microarchitecture and compiler is a must for success in low power research. To this end, we have built a compiler scheme for low power with balance scheduling which is considering about the balances of component utilization in application programs. We could apply variable supply voltages for different components. In this thesis, a solution was proposed to reduce power consumption by compiler to assign the voltage levels of particular components during compilation. There are four phases in our approach. In the first phase, we use traditional compiler tools to get the information of control-flow graph and dependencies, and then we are able to find out the parallel windows of the program. A parallel window is a smaller unit in the basic block and codes are allowed to be executed in parallel. After getting the parallel windows of the program, in second phase, we construct an utilization table which explains the utilization rates of components for each parallel window. In the third phase, two plans for merging parallel windows are proposed. One is to merge those neighboring parallel windows whose utilization rates are similar, another one is to merge those neighboring parallel windows whose sizes are extremely disparate. And in the final phase, a tuning process is used to optimized the solution. Experiments are also done to observe our scheme for reduce power consumption with DAC Alpha 21464 processor. We also demonstrate with our approach for variable voltage scheduling have about twenty to forty percent reduction against the fixed one with variety of benchmarks.