Abstract
To guarantee an application specific integrated circuits (ASIC) meets the timing requirement, at-speed scan testing becomes an indispensable procedure to verify the erformance of ASIC. However, at-speed scan test suffers from the test-induced yield loss. Because, the switching activity in testing is often higher than that in normal function. The switching-induced large current withdrawing in turn causes severe IR drop and increases gate delay. X-filling is the most commonly used technique to reduce IR-drop effect during at-speed test. Nevertheless, none of the existing test relaxation schemes taking the physical location of X-bits into account. Hence it is adversely affecting the effectiveness of reducing switching activities of IR-drop hot zone. In this thesis, we propose a novel test relaxation approach - Physical-Location-Aware X-Identification, which consider the physical information of sensitized scan cells induced switching activities. The experiment results on ITC'99 shows that we have average 42.70% potential transition reduction for the IR-drop hot zone.