Abstract
In order to meet the requirement of short product life cycle, the goal of most semiconductor manufacturing is to reduce its manufacturing cycle time and to deliver products at the right time. Base on Little’s Law, cycle time is proportional to the WIP level, given the same throughput rate. Therefore, in order to reduce the cycle time, the most important thing is to control the WIP. From the Theory of Constraints (TOC), the throughput of a bottleneck workstation is the determinant of the entire fab throughput,so the first step to control the WIP is to set reasonable WIP levels for the bottleneck workstation and the entire Fab, In this study, the bottleneck WIP and the total fab WIP are estimated by using the neural networks, and then the remaining WIP are allocated to other operations . In addition, because of yield consideration, a queue time limit is usually set between two continuous operations, which are called the queue time constraint. If the queue time of a lot exceeds the queue time constraint, the lot will be send back to the previous operation for rework .If the times of rework are too many, a lot may even be discarded. So, before allocating the WIP to each operation, setting a reasonable WIP level for the operations which contain the queue time limit to prevent lots from exceeding the limit is necessary. The WIP levels of operations without time constraint are allocated by using the queueing theory. After setting the standard WIP level of all operations, a dispatching rule to maintain those standard WIP level should be applied. From literature review, there are many useful dispatching rules to reduce the mean cycle time and the standard deviation of the cycle time. But most of them still have some shortages. So in this study, a revised dispatching rule is developed to maintain those standard WIP levels of each workstation and operation, and the mean cycle time and the standard deviation of the cycle time can be effectively reduced.