Abstract
Peak detection and sample-hold (PDSH) circuitry commonly exists voltage droop, pedestal, and overshoot problems. In this work, a PDSH architecture is invented which is operated with a 3V singled voltage and implemented using the TSMC 0.35 micron 1p4m CMOS process.Comparing with previous circuits, we have improved the operational characteristics and the bias condition to prevent voltage droop and overshoot problems when the PDSH circuit is operated in the trace mode and hold mode. Besides, we designed a discriminator circuit to interface the PDSH with an ADC. This circuit can distinguish the input signal from noise; meanwhile, it serves as an input control for the PDSH circuit to avoid the pedestal voltage problem. Simulation results indicated that the PDSH circuit has no voltage droop and pedestal; voltage overshoot is less than 2.5 mV.