Abstract
As the feature sizes in today’s semiconductor process keep shrinking, process variations have greatly influences on the performance of integrated circuits (ICs). Evaluating IC performance before mass production is quite important for quality control. The effects of process variations may result in inconsist circuit timing even for those die in the same wafer, resulting in tremendous yield loss. To know or estimate the extent of the timing variation for an IC before tapped-out which comes from process variations, we have to perform a more detailed simulation such as lithography simulation prior to manufacturing. Typically, these kinds of simulation are extremely slow, so the whole chip simulation is nearly impossible. In this thesis, we provide an alternative that could individually simulate and extract the timing of critical paths without performing whole chip simulation. Also, we have simulated a single cell’s timing variation under different conditions of optical aberrations, which can then be performed on cell based litho. simulation. Besides of timing analysis, it is of equal importance to analyze the layout for locating the hot-spots in advance, which are susceptible to variations or spot defects. Critical area analysis (CAA) is a technique for this purpose that scans and analyzes a layout and reports the critical area for the layout. In this thesis, we will introduce the critical area analysis system that we implemented and use the system to analyze the layout with process variations before and after lithography simulation. With these two techniques, the hot-spots and critical portions of a layout can be identified and fixed at the design stage, shortening the development period for a new design.