Abstract
Traditional virtual cache designs lack of global view of cache hierarchy, TLB and coherenceprotocol. So in most of designs, synonyms are forbidden to appear in virtual caches,and reverse translation mechanism do not take advantage of TLB. This work introduce anew scheme of implementing virtual caches with shared-only TLBs.In our proposed scheme, TLBs are shared by all cores, and enhanced to support reversetranslation, hardware TLB consistency. In addition, synonyms are allowed to present invirtual caches so that it is unnecessary to detect synonym on cache misses, and synonymconsistency is ensured by the coherence protocol with TLB support. Moreover, we developtwo optimizations in which one is a pure hardware solution and the other one requires OSsupport.Finally, we show that by paying 2.5% area overhead, our proposed scheme save 18%dynamic power and reduce 45% TLB misses without harming performance.i