Abstract
In this thesis, we propose a three stage design layout methodology for flip-chip. In stage 1, we use minimum cost flow to produce an initial bumper signal assignment, and then solve the flip-chip floorplanning problem using a partitioned-based technique to spread the modules across the chip. With an anchoring and relocation technique, we can effectively place I/O buffers at suitable locations. Finally, we further reduce signal skew and monotonic routing density by refining the bumper signal assignment. In each stage, we solve the problem in a broader view. Experimental results show that signal skew of traditional floorplanners range from 2% to 280% higher than ours. And the total wirelength of other floorplanners is asmuch as 100%higher than ours. Moreover, the bumper signal refinement after floorplanning can further reduce monotonic routing density and signal skew.