Abstract
In this thesis, we study several parallel process techniques on generating effective DSP code for H.263 video codec. Due to the rapid development of powerful VLIW DSP chips currently, it is possible to accelerate the complex computation of H.263 so that it can generate the compressed video in real time. H.263 is a novel video compression standard in H.324, which is nominated for PSTN communication. H.263 is a block-based coding scheme, uses motion estimation to search the best match block in the reference frame and adopts DCT and quantization to remove the spatial redundancies. It is no surprising that those computations can gain a large degree of parallelism in DSP computation. We use several techniques such as software pipelining, loop unrolling, etc to gain the possible benefit of parallelism.Nowadays, the developing environment of DSP code is getting better due to the progress of complier technology. We simply can write down the code in C and the object code will be generated through code composer automatically. However, in our experience, the efficiency of such DSP execute program is not good quality comparing to the handwritten assembly code because of the weak of parallelism. In this thesis, several computation-intensive procedures were carefully investigated, especially for the possibility of parallelism. Besides, lots of problems, such as allocating function units and registers, settling on delay slots, etc. are all important in generating DSP assembly code. From the experimental results, in general, the execution cycles of assembly code is more less than that generated by the code composer.