Abstract
In this thesis, we developed a practical mixed-level power estimator, named PowerMixer. This tool can take normal circuit formats such as the Verilog netlist and then perform the average power estimation much faster than PowerMill, without losing any noticeable accuracy. It was shown previously that there often exists a statistical correlation between the toggle counts and total power in CMOS logic circuits. The accuracy and run time of PowerMixer strongly relies on the accurate modeling of this correlation. Based on the observation, we experienced a partitioning scheme that divides the logic gates into groups by their respective loading capacitances. An accurate model is then built for each group for future power extrapolation. Experimental results show that such a fine-grained approach indeed achieves a higher accuracy. Less than 1% errors are attained for a number of practical designs, as compared to the results of complete PowrMill simulation.