Abstract
As the evolution of VLSI circuits, manufacturing technology is gradually reduced to 28nm or even 20nm and Back End Of Line (BEOL) metal interconnect wire size is also shrunk to follow Moore’s Law to help the semiconductor industry developing. Shrinking size of BEOL metal Interconnect wire makes the circuit parasitic effect become more significant. Parasitic effects, including resistance, capacitance, and inductance degrade the signal integrity of circuits. Therefore, while the operating frequency keeps increasing to new levels, it is critical to know how to accurate estimate and simulate parasitic effects of BEOL metal interconnect wire. In this thesis, firstly, we use electromagnetic field solver software, SONNET, to extract the scatter parameters by different layers of the signal line and the reference plane of the test structures. Then, the methodology adopted in this research is using formula to transform scatter parameters into RLCG, which is four parameters: resistance (R), Inductance (L), capacitance (C) and conductance (G). Meanwhile, various combinations of the four parameters: RLCG can also establish different time-domain models of transmission line, such as RC, RLC and RLCG. Also, we use HSPICE to transform time-domain model into scatter parameters, which can be applied to verify scatter parameter and time-domain model. Finally, we implement a graphical interface software which offers two modes to help users to save time for circuit design. One of the modes is that users input operating frequency, width, length and test structure of wire, and then RLCG values and characteristic impedance (Z0) will be generated. Another mode is program reading data from frequency with scatter parameters, and libraries and graph and the values of RLCG with frequency will be generated.