Abstract
With the eager demand of light, thin, and high performance of portable electronic devices, it has been a trend for miniaturizing the structure packaging to integrate the system chip. However, the interior structure of the portable electronic devices could be destroyed as the portable electronics devices are subjected to severe impact due to the conveyance and careless drop. Therefore, it becomes an important issue for the development of advanced packaging to enhance the drop impact resistance of devices. The three-dimensional (3D) Chip-on-Chip (CoC) Stacking Package receives great attention because of its ability to miniaturize the package, to significantly shorten the interconnect pitch, and to enhance electronic signal transmission efficiency. By the numerical simulation method and the experimental validation, this work aims to study the drop impact reliability of the ultra-fine-pitch 3D CoC Stacking Package which is developed by ITRI. This package consists of a top chip, a bottom chip and 3,216 Cu/Ni/SnAg I/O micro bumps. Because the pitch and size of micro bumps are much smaller than conventional package, it is crucial to pay more attention to its drop impact reliability. The standard JEDEC（Joint Electron Device Engineering Council) specification is adopted in the drop impact test. As the drop table of drop impact tester freely falls, it produces an almost half-sine wave acceleration function, and its peak acceleration and impulse time are 1,500G and 0.5 ms respectively. As for the numerical simulation, the LS-DYNA finite element software is applied to create an accurate and reliable 3D finite element analysis model. To well simulate the dynamic responses of the micro bumps, a Johnson-Cook constitutive model, which takes into account the effects of strain rate and temperature, is employed, and the input-G method is applied for simulating the dynamic loading. The calculated results of 3D FE modeling match very well with the experimental data. To evaluate the drop impact fatigue life of the micro bump, this work further systematically carries out a set of drop impact fatigue life experiments under different drop test conditions. Besides, through the optical microscope inspection, it is found that the failure area of micro bumps all occur at the SnAg zone. Based on the obtained fatigue test data and the strain energy density of SnAg of micro bump computed through FE analysis, a Darveaux drop impact fatigue life prediction equation is successfully constructed in this work. Finally, to provide a reference for promoting the drop impact fatigue life resistance for 3D CoC Stacking Package, the effects of different SnAg solders, underfill, IMC thickness ratio and the thickness of the top and bottom chip are investigated through the parametric study.