Abstract
With the advanced VLSI technology, sharp slew rate and low power comsumption are often required in integrated circuit design. Timing buffering on non-critical nets may result in extra power dissipation and waste of buffering resource. Unfortunately, most previous works still optimized for delay instead of handling the slew constraints independently. For the related works, [7] proposed an equation to model slew while [5] used a capacitance-based slew model without considering interconnect resistivity. In this paper, the elementary problem of simultaneous routing and buffer insertion for two-pin nets is studied. We propose two optimal polynomial time algorithms for maze routing with minimum cost buffer insertion under slew and obstacle constraints and we employ two different slew models in our algorithms. Besides minimizing power/total buffer size, our algorithms can also be adapted to handle other buffering costs. It is more than an order of magnitude faster than maze routing with buffer insertion for optimal delay [2]. Experimental results demonstrate that our MCSB algorithm is very efficient and the runtime is insensitive to the slew constraints.