Abstract
Germanium (Ge) is proposed as promising channel material in metal oxide semiconductor field effect transistor (MOSFETs) for next generation, because its electron and hole mobility are both higher than Si, which are about two and four times higher, respectively. However, there are many challenges to use Ge material. Ge oxide is easily volatilized and hydrolyzed at high temperature. Ge diffusion into gate dielectric would induce gate leakage, and Ge oxide quality for interfacial layer is a critical engineering. These issues should be resolved as the first priority. Besides, the root cause of leakage currents in device and temperature sensitivity of Ge substrate are not clear yet. Therefore, different high-K thicknesses are deposited to form devices with higher and lower gate leakage current in this thesis. Then, the root cause of leakage currents from gate or junction may be clarified. Next, the leakage currents in Ge MOSFETs could be suppressed by annealing treatments at optimal temperature. Ge MOSFETs with excellent characteristics and ultralow Equivalent Oxide Thickness (EOT) are hopefully obtained. Reduced leakage current and improved electrical characteristics in Ge MOSFETs would be achieved by sintering at suitable temperature. In the first part, the root causes of leakage currents in Ge MOSFETs with various high-K thicknesses are studied. Sample with 2.5 nm thick HfON shows the electrical thickness in inversion (Tinv) of 6.5 Å and higher gate leakage. Sample with 5 nm thick HfON presents Tinv of 10 Å and lower gate leakage, which however has large off-state currents in Ge MOSFET. These results indicate that the junction leakage current is the root cause of leakage currents in Ge MOSFET, since the off-state current could not be decreased by a thicker high-K with lower gate leakage. In the second part, a 3 nm thick HfON is grown by an Atomic Layer Deposition System (ALD), to obtain an ultralow EOT. Next, source and drain regions is formed by BF2 implantation, and a Rapid Thermal Annealing (RTA) is performed to reduce junction leakage. As a result, junction leakage current of 1.17 x 10^-6 A at reverse bias of - 0.5 V in Ge P-MOSFETs can be obtained by a RTA at 450℃ for 30s. Experimental results show that off-state current of 2.56 x 10^-9 A/um is obtained, sub-threshold swing (S.S.) is reduced to 136 mV/dec, and the On/Off ratio is increased to 10^4. The gate leakage current is decreased to 2.58 x 10-4 A/cm2, because there are more Ge3+ in the interfacial layer. Peak hole mobility of 375 cm2/V-sec is achieved by a RTA at 450℃. In the third part, different sintering temperatures on Ge MOSFETs are studied with the optimal RTA condition in previous works. Device with low junction leakage current, low gate leakage current, low EOT, and high mobility may be obtained. Junction leakage current is increased to 1.38 x 10^-6 A at reverse bias of - 0.5 V in device with sintering at 400℃ for 30 min. The off-state current is obtained 2.95 x 10^-9 A/um, which might degrade device characteristics. However, transconductance (Gm) could be improved in Ge P-MOSFETs. On the other hand, a lower sintering temperature, for example 300℃, 350℃, would decrease junction leakage but Gm is decreased.