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通道摻雜及低溫沉積介電層對多晶鍺無接面快閃記憶體元件特性研究
Thesis

通道摻雜及低溫沉積介電層對多晶鍺無接面快閃記憶體元件特性研究

周冠圻
Masters, 國立清華大學, 工程與系統科學系
2015

Abstract

多晶鍺 無接面 快閃記憶體 通道摻雜 poly Ge junctionless flash memory channel dopant
The scale down of planar flash device is limited by its capability of micro-miniature, which makes the process flow more complex. How to improve the electrical characteristics and increase the device density at the same time becomes two of the most important issues. Some approaches have been reported such as the implement of high-k materials, nanowire channel structure, junctionless channel, poly-Si channel and SiGe buried channel. The carrier mobility of Ge is higher than that of Si. poly-Ge devices can be fabricated at low temperature process (<600˚C), which can reduce process thermal budget. Poly-Ge film is naturally p type without any implantation. There is no report about the effect of channel dopant on poly-Ge. In this thesis, we implement poly-Ge on junctionless channel flash memory devices, and the characteristics of channel dopant are investigated. The low temperature process was achieved by ICPCVD. In the first experiment, the characteristics of channel dopant on poly-Ge junctionless flash memory are investigated. The results show that doped poly-Ge devices perform better on program/erase speed, retention, and endurance. The poly-Ge device with N type dopant perform better because the main carriers of channel are electrons. The injection current of program/erase is higher and the interface states between channel and tunneling layer are fewer. In the second experiment, to improve the characteristics of poly-Ge flash memory, low temperature formed Si3N4 is applied to N channel poly-Ge flash memory device. The HfO2/Si3N4 stacked charge trapping layer perform better on program/erase speed. Furthermore, the Si3N4 layer improve retention performance because of high energy barrier. In the third experiment, the characteristics of poly-Ge and poly-Si devices with low temperature process by using HfO2/Si3N4 stacked charge trapping layer are investigated. The poly-Si device performs better on program/erase speed because of thinner tunneling oxide and smaller channel dimension. The N channel poly-Ge device performs better because the main carriers of channel are electrons. The injection current of program/erase is higher and the interfaces state between channel and tunneling layer are fewer. The P channel poly-Ge performs better on on/off ratio and transistor characteristics because of better channel interface of P channel poly-Ge device.

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