Abstract
ABSTRACT In modern communication systems, the interference of the channel noise is unavoidable when we transmit data. To overcome this problem, many theories about channel coding have been developed. Firstly, the data in the transmitter is coded, and then transmitted to the receiver via channel. Though it may be corrupted by the channel interference, the decoder can still get the decoded data that is like the original data. The most commonly used error control coding is the convolutional code in communication systems. The Viterbi algorithm is a Maximan-likelihood decoding algorithm for the convolutional code. When developing the channel decoder without hardware support, we can only use software tools such as Xilinx ISE, Synplify Pro, or ModelSim to synthesize and simulate the decoder. In this thesis, we first design a PCI-based emulation hardware and host GUI system that utilizes a Xilinx FPGA XCV1000E for fast design realization and real-time emulation for channel decoder. Users can compiler their decoder circuit and use the system to program decoder circuit into the FPGA quickly. The system can generate convolutional code continuously, add the simulated channel noise, and then transmit data to decoder circuit by PCI interface. The system can then analyze the results from the FPGA decoder to test and verify if the design is correct.Besides, a flexible IP builder is designed which enables experimenting different aspects of Viterbi decoders by changing (n,k,m) parameters. The builder can generate the VHDL code of different parameter according to our need. Afterward, the real-time hardware emulation of the decoder can be performed.The field test of the developed PCI-based FPGA hardware emulation platform illustrates the effectiveness and usefulness of the system. It can also be used as a general fast hardware emulation platform for designing other circuits and applications.