Abstract
The performance of digital processor depends on the speed of adder. In the past, high-speed adders have been continuous invented. Among that, CLA (Carry Look Ahead Adder) was the most well known high-speed adder. In recent years, an improved version of CLA called MCLA (Modified Carry Look Ahead Adder) was presented. However, carry propagation was still the bottle neck in both CLA and MCLA. In this thesis, a new type adder called CT-MCLA (Carry Through - Modified Carry Look Ahead Adder) is proposed to improve the carry propagation issue and uses less area. Combined MCLA, the proposed adder uses the carry through technique to overcome carry propagation issue for obtained higher speed. The simulation results of proposed CT-MCLA from 8-bit to 64-bit improve area of 5~10% compared with MCLA. The speed is improved –6%~9%. The product of area size and time square (AT2) is also improved 3~14%.