Abstract
Semiconductor fabrication has the characteristics of short manufacture’s life cycle and high production costs. It is therefore considerably important to boost the production yield rate in order for the enterprises to profit. Among manufacturing costs, 95% is affected by design, thus the earlier one finds the influence the better. Integrated circuits（IC）are composed of many overlapping layers, thus irregular topography will leave the surface of ICs during fabrication. Chemical mechanical polishing（CMP）removes material and tends to even out any irregular topography, making the wafer planar; this is necessary in order to bring the entire surface within the depth of field of a photolithography system. The most significant problem arises when polishing is “dishing”, which is a form of local planarization where areas of the wafer are polished faster than others. To solve this problem, the common practice is to design dummy feature into the dies such that the variability of the circuit density can be reduced and the dishing problem can be eliminated. This research focuses on efficient dummy feature placement. First, simulate the IC’s data map. Second, calculate the density of the simulated data. Third, use fuzzy C-means to cluster the data with similar density into the same group for lowering the complexity of huge databases. And finally, place dummy feature into low circuit density data groups by self-generated homogenization methods and then analysis the results. The calculation can come from the results in less than 1 minute and lower the variability of density by 49% and 69% respectively via different parameter settings which fulfill the research purpose.