Abstract
Flip chip process is a mature assembly techniques used in the packaging industry for consumer products today. The IC product size of this assembly technology is quite small that can reduce the device volume. The key technique in the flip chip process is bumping process which is generated the solder bump on IO pad of the wafer via electrochemical plating. In the past, the composition of the metal was high-lead or lead-solder eutectic metallization. Today, most firms follow with environmental ROHS regulations; majority customers required their product to adopt silver soldering material in recent years. Electrical device’s life cycle is much shorter nowadays, product development timeline become a challenge task for quality yield and product launch timing. Firms spent a lot of time and dummy test for parameter fine tune during the bumping new-product-introduce stage. In the past, engineer searched for historical data to set the parameter but it needs a long time and with high cost. In this study, we provide an approach which demonstrate a back-propagation network to construct a prediction model by using the historical data and the performance by data and actual in-line enhancement to verify the benefit of time and cost saving by this method.