Abstract
The process of semiconductor fabrication is very complex and it needs expensive materials, precise machines and high-standard environment for production. Semiconductor industry has the characteristics of high cost and low life cycle, so how to enhance yield such that the manufacturing cost can be reduced has become one of the most important issues. Finding out the factors which will affect yield and involving the production design engineer to consider these influence factors in the design phase is a good method to improve yield.The purpose of the Chemical Mechanical Polishing (CMP) process is to planarize heights caused by the deposition of thin films over existing nonplanar features such that further levels may be added onto a flat surface. If there is no flat surface, it is unable to photolithography the line on the surface. Dish effect is due to the fact that the pad exerts different stresses upon the wafers. Because the variability of the circuit density, it will decrease the planarity of the wafer surface. Caves and defects may therefore be formed after the CMP process. To solve this problem, it is necessary to insert dummy circuits into low-density layout regions such that the variability of the circuit density can be reduced, the dish effect can hopefully be eliminated and yield can be increased at the same time.The objective of dummy circuits is to make pattern density more uniform across a die. This research focuses on how to insert dummy circuits in original circuit layout to increase the circuit density, improve the planarity of the wafer surface, and therefore improve the yield. Through an efficient algorithm, it is possible to find out an appropriate method of inserting dummy circuits. And it can improve the variability of the circuit density and uniformize the stresses exerted upon the wafer in the process of CMP. It is expectable that the failure will be reduced in the process of CMP. Besides, we want to reduce the complexity of data analysis. So we use a circuit layout diagram as a Blue Print to perform a two-stage clustering analysis which can reduce the complexity of the data. And then we use Mathematical Optimization method to solve the optimizing dummy circuits problem under a current circuit design.In this research, we use a circuits diagram provided by a semiconductor enterprise. Through a two-stage clustering analysis and mathematical optimization method, we insert dummy circuits into low-density layout regions. The results show that this method can successfully increase the density of the circuits and reduce the standard deviation of density.