Abstract
In this thesis, standard specification study, functional simulation, architecture design and circuit design along with FPGA implementation of a multiple coding rates LDPC decoder for IEEE 802.11n communication systems is presented. In order to achieve the high data rate requirement, several decoding algorithms are discussed. As considering the construction of the parity check matrices and the decoding convergence speed, we chose "Layered Belief Propagation Algorithm" as decoding algorithm. Besides, it can also save some memory resources since the messages need to store are less than the conventional decoding algorithm "Log-Likelihood Ratio Sum Product Algorithm". Furthermore, the use of min sum algorithm sacrifices acceptable performance loss but reduces the large computational complexity while doing the update the messages during the iterative decoding process. In addition to processing different modulation types, a soft de-mapper is also constructed to provide log likelihood ratio for LDPC decoder to do the decoding procedure. In system performance simulation, we apply the additive white Gaussian noise (AWGN) as the channel impairments to estimate our decoding performance under several different modulation types and coding rates. In the worst case of the system simulation which is under 64-QAM and coding rate 5/6, the BER is under 10-6 at SNR less than 14.5dB. On the other hands, the system simulation with BPSK modulation and coding rate 1/2 is the best case whose BER is under 10-6 at SNR about 3.75dB. The proposed LDPC decoder and soft de-mapper are implemented by FPGA system broad whose FPGA model is Virtex-4 XC4VLX60-FF668. The maximum clock frequency can reach 116.15MHz and the estimated maximum data rates for different coding rates all meet the data rate requirement of the specification.