Abstract
In this thesis, a SIP design and verification of a baseband transceiver that complies with IEEE 802.16-2004 standard OFDM PHY layer is presented. The proposed baseband transceiver IP supports BPSK, QPSK, 16-QAM, and 64-QAM modulation as well as four different CP length ratio. The IP uses 20 MHz channel bandwidth and supports maximum coded data rate up to 92.16 Mbps. The proposed baseband transceiver IP consists of several functional blocks such as timing synchronization, frequency synchronization, FFT, channel estimation, equalization, phase tracking, and demodulation. The design flow of the baseband transceiver IP starts from system specification study, architecture de‾nition, and performance evaluation. The following steps consists of logic design, functional simulation, coding style check, code coverage analysis. The next steps are logic synthesis and gate-level simulation. Last and most specially of all steps are the FPGA prototyping and emulation. The baseband transceiver IP is synthesized in TSMC 0.13 ¹m 1p6m technology. The maximum operating clock rate of transmitter is 40 MHz, and the maximum operating clock rate of receiver is 25 MHz. The power consumption of transmitter and receiver are about 9 mW and 75 mW respectively. Simulation results and emulation results present correct function and satisfactory performance of the baseband transceiver IP.