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適用於以正交分頻多工為基礎無線個人網路系統之高輸出率與高硬體效率快速傅立葉轉換/ 反快速傅立葉轉換處理器
Thesis

適用於以正交分頻多工為基礎無線個人網路系統之高輸出率與高硬體效率快速傅立葉轉換/ 反快速傅立葉轉換處理器

蔡睿偉
Masters, National Tsing Hua University
2009

Abstract

無線個人網路正交分頻多工快速傅立葉轉換多路徑延遲回授多資料進位 WPANOFDMFFTMDFmulti-data scaling
Wireless personal area network (WPAN), currently under development by IEEE 802.15.3c Task Group, targets to provide multi-giga bits per second (multi-Gbps) data rate for the short-distance and ultra-high speed communication technology in the next generation. The high-speed interface (HSI) mode defined in this standard adopts orthogonal frequency division multiplexing (OFDM), which, with great bandwidth efficiency and invulnerability to non-ideal channel, is regarded as a prospective modulation strategy. Its specifications, however, impose a great challenge on the design of its key component, a long-length and high-throughput-rate Fast Fourier Transform (FFT) processor with acceptable hardware cost. In this thesis, we proposed a high throughput-rate and hardware-efficient 2048-point FFT/IFFT processor, in which the number of parallel paths is extended from four to eight.Besides, an efficient memory-accessing scheme and a novel constant-based multiplier unit are also proposed to reduce both area and power consumptions resulted from doubled data-path numbers. Also, a new multi-data scaling method is proposed, which can be easily integrated with multi-path delay-feedback (MDF) architecture using relatively simple control logic. The proposed FFT/IFFT processor is implemented in UMC 90-nm 1P9M process, whose core area is 1.18 mm2 and power consumption is 127 mW at 300MHz operating frequency. Compared with previous four-path architecture, the proposed processor has only 21.6% more area cost and provides up to 2.4G sample/s throughput rate at only 8.5% more power consumption. Moreover, a test chip of 128-point FFT processor is fabricated using UMC 90-nm 1P9M process to verify the high throughput-rate and hardware-efficiency of our architecture. This test chip has a core area of 0.53 mm2, a power consumption of 6.8 mW at 52 MHz operating frequency, and a maximum throughput rate of 2.08G sample/s. Therefore, the proposed 2048-point FFT/IFFT processor is a promising solution to the realization of OFDM-based WPAN systems in the future.

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