Abstract
In new generation wireless communication system, quasi-cyclic low-density parity-check code is popularly used in WiMAX and fit into Standard Performance Evaluation Corporation(SPEC) of 802.16e. They provide performance that comes quite close to the Shannon limit. With the advanced technology, implementing LDPC code decoder is not an impossible thing and there are more and more researches on LDPC codes. There are also many communication systems adopt LDPC codes as their channel coding, such as 802.11n and 802.16e. Although LDPC codes have excellent decoding performance, realizing it is never an easy job. There still exist many challenges when implementing LDPC code decoder. The high routing complexity, large chip area and high power consumption all need to take into concerns. In our paper, we proposed a decoder architecture which is focused on fast convergence speed. Since the lower calculating unit is used, we need longer calculating time. We use pipeline method to improve throughput efficiently. a new method of memory access is proposed to avoid hazards in accessing values of a posteriori probability from memories. This paper use 0.18um^2 1p5m to implement 1/2 code rate LDPC of IEEE 802.16e. At 200 MHz, the throughput can achieve 105Mbps(not include io pad delay). The core area is 2.38x2.38mm^2. The routing-problem can be solved by the proposed architecture, so the proportion of routing is about 30% of total area, and can support multi code length decoding. The design of chip is used ASIC flow. First, we write RTL code. Then, we synthesize our code. After various simulating, we verify result. We prove our whole system architecture is correct.