Abstract
This work presents a 10Ks/s 10-bit successive approximation analog-to-digital converter which is realized in a 0.35um CMOS process. The design combines an input offset storage latch-comparator, a sample and hold, a resistor-capacitor array DAC, and SAR digital logic while consuming less than 720uW with a 3.0V power supply. The experimental results show that the effective number of 7.61 bits with 10Ks/s and 100Hz signal frequency. Main purpose of the whole circuit is integrating into CMOS MESMS accelerometer and IIC interface circuit.